module decoder(
	input				clk_in,
	input				rst_n,

	input		[31:0]	Addr,
	output	reg	[31:0]	RdData,
	input		[31:0]	WrData,

/*--------------------------------CH0--------------------------------*/
	output	reg	[15:0]	CH0_addr,
	output	reg	[31:0]	CH0_data_w,
	input		[31:0]	CH0_data_r,

/*--------------------------------CH1--------------------------------*/
	output	reg	[15:0]	CH1_addr,
	output	reg	[31:0]	CH1_data_w,
	input		[31:0]	CH1_data_r,

/*--------------------------------CH2--------------------------------*/
	output	reg	[15:0]	CH2_addr,
	output	reg	[31:0]	CH2_data_w,
	input		[31:0]	CH2_data_r,

/*--------------------------------CH3--------------------------------*/
	output	reg	[15:0]	CH3_addr,
	output	reg	[31:0]	CH3_data_w,
	input		[31:0]	CH3_data_r,

/*--------------------------------DIG--------------------------------*/
	output	reg	[15:0]	dataIn_code,
	output	reg	[9:0]	wr_addr_code,
	output	reg			wr_en_code,
	output	reg	[31:0]	data_range,
	output	reg	[31:0]	pulse_range,
	output	reg	[9:0]	max_addr,
	output	reg			code_rst_n,
	output	reg	[13:0]  dioin,
	output	reg			dinaclr,
	output	reg			rd_code,
	input		[1:0]   DIO_IN,
	output	reg			clkselect,
	
	input				VT_st,
	output	reg			VerusTrigger,
	output	reg			VT_gt,
	output	reg [1:0]	TriggerMode,
	output	reg [3:0]	TriggerDNum,

	output	reg	[31:0]	test_port

);

always@(posedge clk_in)
begin
	if(!rst_n)
	begin
		test_port	<= 32'h0;
		CH0_addr	<= 16'h0;
		CH0_data_w	<= 32'h0;
		VerusTrigger<= 1'b0;
		VT_gt		<= 1'b0;
		clkselect	<= 1'b0;
	end
	else
	begin
		case(Addr[15:0])
/*--------------------------------WRITE--------------------------------*/
/*--------------------------------WRITE--------------------------------*/
/*--------------------------------WRITE--------------------------------*/
		16'h1001:begin
				test_port	<= WrData;
			end

/*--------------------------------CH0--------------------------------*/
//上位机向底板写数据
		16'h1101:begin
				CH0_addr	<= 16'h1001;
				CH0_data_w	<= WrData[15:0];
			end
		16'h1102:begin
				CH0_addr	<= 16'h1002;
				CH0_data_w	<= WrData;
			end

//上位机从底板读数据
		16'h1103:begin
				CH0_addr	<= 16'h0001;
				CH0_data_w	<= WrData[15:0];
			end

/*--------------------------------CH1--------------------------------*/
//上位机向底板写数据
		16'h1201:begin
				CH1_addr	<= 16'h1001;
				CH1_data_w	<= WrData[15:0];
			end
		16'h1202:begin
				CH1_addr	<= 16'h1002;
				CH1_data_w	<= WrData;
			end

//上位机从底板读数据
		16'h1203:begin
				CH1_addr	<= 16'h0001;
				CH1_data_w	<= WrData[15:0];
			end

/*--------------------------------CH2--------------------------------*/
//上位机向底板写数据
		16'h1301:begin
				CH2_addr	<= 16'h1001;
				CH2_data_w	<= WrData[15:0];
			end
		16'h1302:begin
				CH2_addr	<= 16'h1002;
				CH2_data_w	<= WrData;
			end

//上位机从底板读数据
		16'h1303:begin
				CH2_addr	<= 16'h0001;
				CH2_data_w	<= WrData[15:0];
			end

/*--------------------------------CH3--------------------------------*/
//上位机向底板写数据
		16'h1401:begin
				CH3_addr	<= 16'h1001;
				CH3_data_w	<= WrData[15:0];
			end
		16'h1402:begin
				CH3_addr	<= 16'h1002;
				CH3_data_w	<= WrData;
			end

//上位机从底板读数据
		16'h1403:begin
				CH3_addr	<= 16'h0001;
				CH3_data_w	<= WrData[15:0];
			end

/*--------------------------------DIG--------------------------------*/
		16'h1501: begin
				data_range	<= WrData;
		end
		16'h1502: begin
				pulse_range	<= WrData;
		end
		16'h1503: begin
				wr_addr_code	<= WrData[25:16];
				dataIn_code		<= WrData[15:0];
		end
		16'h1504: begin
				wr_en_code		<= WrData[0];
		end
		16'h1505: begin
				max_addr		<= WrData[9:0];
		end
		16'h1506: begin
				code_rst_n		<= WrData[0];
		end
		16'h1507: begin
				dioin			<= WrData[13:0];
		end
		16'h1508: begin
				rd_code			<= WrData[0];
		end
		16'h1509: begin
				dinaclr			<= WrData[0];
		end
		16'h150A: begin
				clkselect		<= WrData[0];
		end


/*--------------------------------Trig--------------------------------*/
		16'h1601: begin		//底板读完64通道后发1
				VT_gt	<= WrData[0];
		end
		16'h1602: begin		//底板读完64通道后发1
				VerusTrigger	<= WrData[0];
		end
		16'h1603: begin		//底板读完64通道后发1
				TriggerMode		<= WrData[1:0];
		end
		16'h1604: begin		//判定触发通道所在槽
				TriggerDNum		<= WrData[3:0];
		end
		
/*--------------------------------READ--------------------------------*/
/*--------------------------------READ--------------------------------*/
/*--------------------------------READ--------------------------------*/
		16'h0001:begin
				RdData	<= test_port;
			end
/*--------------------------------CH0--------------------------------*/
		16'h0101:begin
				CH0_addr	<= 16'h0002;
				RdData		<= CH0_data_r;
			end
/*--------------------------------CH1--------------------------------*/
		16'h0201:begin
				CH1_addr	<= 16'h0002;
				RdData	<= CH1_data_r;
			end
/*--------------------------------CH2--------------------------------*/
		16'h0301:begin
				CH2_addr	<= 16'h0002;
				RdData	<= CH2_data_r;
			end
/*--------------------------------CH3--------------------------------*/
		16'h0401:begin
				CH3_addr	<= 16'h0002;
				RdData	<= CH3_data_r;
			end
			

/*--------------------------------DIG--------------------------------*/		
		16'h0501: begin
				RdData	<= {30'h0,DIO_IN};
		end

/*--------------------------------TRIGGER--------------------------------*/
//上位机监听触发状态，完成置1，未完成置0
		16'h0601:begin
				// RdData	<= {31'h0,1'b0};
				RdData	<= {31'h0,VT_st};
			end
		default:
            begin
				RdData	<= RdData;
				
				test_port	<= test_port;

				CH0_addr	<= CH0_addr;
				CH0_data_w	<= CH0_data_w;

				CH1_addr	<= CH1_addr;
				CH1_data_w	<= CH1_data_w;

				CH2_addr	<= CH2_addr;
				CH2_data_w	<= CH2_data_w;

				CH3_addr	<= CH3_addr;
				CH3_data_w	<= CH3_data_w;
            end
		endcase

	end
end

endmodule
